Aishik Bandyopadhyay — AI Engineer & Data Scientist

AI Engineer & Data Scientist

Peer-reviewed FPGA edge inference (IEEE ISVLSI 2026), multi-agent LLM orchestration, and algorithmic fairness systems — research-grade AI shipped end to end.

Aishik Bandyopadhyay
Based in Kolkata, West Bengal, India

Selected Work

YOLOv11-Nano on FPGA

University of Calcutta · IEEE ISVLSI 2026

Edge Inference Acceleration · Jan 2025 – Present

  • First peer-reviewed YOLOv11 DPU deployment — accepted as full paper at IEEE ISVLSI 2026.
  • 25.77 FPS on ZCU104 (+49% throughput) and 38.81 ms latency (−33%) vs Intel i5-12650H.
  • Collapsed 9 fragmented DPU subgraphs to 1 via operator substitution (SiLU→ReLU, Softmax→HardSigmoid, matmul→element-wise).
  • Demonstrated hand-curated 250-image calibration outperforms random 1300-image sets under INT8 quantisation.
Vitis AIXilinx ZCU104DPUCZDX8GINT8 QuantizationPythonPYNQ
25.77 FPS
+49% throughput vs CPU

Veritas

IEEE Transactions on Technology and Society (manuscript in preparation)

Algorithmic Fairness Auditing Framework · 2024

  • End-to-end framework auditing ML classifiers across disparate impact, statistical parity difference, equalized odds, and Theil index simultaneously.
  • Comparative mitigation framework enabling evidence-grounded intervention selection across pre-, in-, and post-processing stages.
PythonAIF360fairlearnRAGNIST AI RMFEU AI Act
IEEE TTS
manuscript in preparation

CAG + GraphRAG Agentic Pipeline

Knowledge-intensive NLP with sub-second latency · 2024

  • Neo4j GraphRAG retrieval combined with Cache-Augmented Generation (CAG) targeting sub-second inference.
  • KV cache persistence via DynamicCache + pickle serialisation; ablated structured vs. flat RAG baselines.
Neo4j Aura DBTinyLlamaKV Cache PersistencePythonLangChain
All projects →

Let's build something

Available for collaborations.

official.aishik109@gmail.com